View DS26502DK_285605.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DS26502DK T1/E1/J1/64KCC Bits Element Design Kit
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26502DK is an easy-to-use evaluation board for the DS26502 T1/E1/J1/64KCC BITS element. The DS26502DK is intended to be used as a standalone design kit. The board is complete with a DS26502 BITS element, transformers, termination resistors, FPGA-based configuration switches, and network connectors. Dallas' ChipView software gives point-and-click access to configuration and status registers from a Windowsa-based PC. On-board LEDs indicate receive loss-of-signal and interrupt status as well as multiple clock and signal routing configurations.
Windows is a registered trademark of Microsoft Corp.
FEATURES

Expedites New Designs by Eliminating First-Pass Prototyping Demonstrates Key Functions of DS26502 BITS Element Includes DS26502 BITS Element, Transformers, BNC, and RJ48 Network Connectors and Termination Passives BNC Connections for 75W E1 Bantam and RJ48 Connectors for 120W E1 and 100W T1 Interface Directly to IBM-Compatible Computers High-Level Software Provides Visual Access to Registers ChipView Software Provides Point-and-Click Access to the DS26502 Register Set Software Controlled (Register Mapped) Configuration Switches to Facilitate Clock and Signal Routing All Equipment-Side Framer Pins are Easily Accessible for External Data Source/Sink LEDs for Loss-Of-Signal and Interrupt Status as well as Indications for Multiple Clock and Signal Routing Configurations Easy-to-Read Silk Screen Labels Identify the Signals Associated with All Connectors, Jumpers, and LEDs
DEMO KIT CONTENTS
DS26502DK Design Kit CD_ROM Including:

* * * *
ChipView Software DS26502DK Data Sheet DS26502 Data Sheet DS26502 Errata Sheet (if applicable)
ORDERING INFORMATION
PART DS26502DK DESCRIPTION Stand-Alone Design Kit for DS26502
1 of 30
REV: 030705
DS26502DK
COMPONENT LIST
DESIGNATION C1, C23, C51, C53 C2-C4, C6-C9, C11, C12, C14, C15, C17, C18, C20, C21, C25-C30, C32, C33, C35, C36, C38, C45-C50, C52, C54, C55, C57-C60, C62, C63, C68 C5, C10, C22, C24, C31, C34, C37, C39-C41, C43, C65-C67, C69, C70 C13, C19, C42, C44, C64 C16, C56, C61 D1 DS1, DS2, DS6-DS9 DS3 DS4 DS5 DS10 J1 J2 J3, J6-J8 J4 J5 J9 J10, J11 J12, J13 JP1, JP3-JP8 JP2 L1 NP1, NP2 R1, R8-R11 R2, R13, R23, R27, R43, R47, R67-R70 QTY 4 DESCRIPTION 10mF 20%, 10V ceramic capacitors (1206) SUPPLIER Panasonic PART ECJ-3YB1A106M
42
1mF 10%, 16V ceramic capacitors (1206)
Panasonic
ECJ-3YB1C105K
16 5 3 1 6 1 1 1 1 1 1 4 1 1 1 2 2 7 1 1 2 5 10
0.1mF 20%, 16V X7R ceramic capacitors (0603) 10mF 20%, 16V tantalum capacitors (B case) 68mF 20%, 16V tantalum capacitors (D case) 1A 50V general-purpose silicon diode LED, RED, SMD LED, GREEN, SMD LED, AMBER, SMD LED, GREEN, SMD (Not populated) LED red/green, 5mm red/green right-angle PCMT Socket, banana plug, horizontal, black Socket, banana plug, horizontal, red Terminal strip, 16-pin, dual row, vertical DB9 right-angle, long case connector L_CONNECTOR BNC 75W vertical 5-pin L_RJ48 8-pin,single-port connector BNC connectors, 75W right-angle 5-pin L_CONN, Bantam jack, right-angle 100-mil, 2 position jumper 14-pin header, remove 'missing pin' Inductor, 22.0mH 2-pin SMT 20%
AVX Panasonic Panasonic General Semiconductor Panasonic Panasonic Panasonic Panasonic Digi-Key Mouser Electronics Mouser Electronics Samtec AMP Cambridge MOLEX Kruvand Switchcraft labstock labstock Coiltronics
0603YC104MAT ECS-T1CX106R ECS-T1CD686R 1N4001 LN1251C LN1351C LN1451C LN1351C 350-1055-ND 164-6218 164-6219 TSW-108-07-T-D 747459-1 CP-BNCPC-004 15-43-8588 UCBJR220 RTT34B02
UP1B-220 1206CG100J9B200 ERJ-8GEYJ0R00V ERJ-3GEYJ331V
10pF 5%, 50V tall case ceramic capacitors (1206) Phycomp Do not populate Panasonic 0W 5%, 1/8W resistors (1206) 330W 5%, 1/16W resistors (0603) Panasonic
2 of 30
DS26502DK
DESIGNATION R3, R18-R20, R22, R25, R26, R28-R31, R33-R42, R44-R46, R49, R50, R53, R56, R59, R61, R62, R65, R72 R4, R5, R48, R51, R54, R55, R57, R58 R6, R7 R12 R14-R17, R21, R24, R63, R64, R66, R71 R32 R52 R60 SW1, SW3 SW2 T1 TP1, TP2 TP3-TP10 U1 U3, U6 U4 U5 U7 U8, U9, U13 U10 U11 U12 U14 X1 Y1 Y2 Y3 QTY DESCRIPTION SUPPLIER PART
33
10kW 5%, 1/16W resistors (0603)
Panasonic
ERJ-3GEYJ103V
8 2 1 10 1 1 1 2 1 1 2 8 1 2 1 1 1 3 1 1 1 1 1 1 1 1
30W 5%, 1/16W resistors (0603) 61.9W 1%, 1/8W resistors (1206) 51W 5%, 1/16W resistor (0603) 1.0kW 5%, 1/16W resistors (0603) 1.0kW 5%, 1/10W resistor (0805) 51.1W 1%, 1/10W resistor (0805) 1.0MW 5%, 1/16W resistor (0603) Switch MOM 4-pin single pole Switch 8-position, 16-pin DIP, low profile XFMR 16P SMT Testpoint, 1 plate thru-hole Testpoint, 1 plated hole DO NOT STUFF 32-bit microcontroller (lab stock) SRAM 5V, 1Mb SO (in lab stock) Xilinx Spartan 2.5V FPGA, 20mm x 20mm 144-pin TQFP 8-Pin mMAX/SO 2.5V or Adj 64-pin LQFP T1/E1/J1 BITS element (0C to +70C) High-speed inverter High-speed buffer Dual RS-232 transceivers with 3.3V/5V internal capacitors 1Mb flash-based config mem 8-pin SO step-up DC-DC converter 0.5A limit Low-profile 8.0MHz crystal Oscillator, crystal clock, 3.3V, 6.312MHz Oscillator, crystal clock, 3.3V, 2.048MHz Oscillator, crystal clock, 3.3V, 1.544MHz
Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic AMP Pulse NA NA Avnet Cypress Xilinx Maxim Dallas Semiconductor Fairchild Fairchild Maxim Xilinx Maxim PEI SaRonix SaRonix SaRonix
ERJ-3GEYJ300V ERJ-8ENF61R9V ERJ-3GEYJ510V ERJ-3GEYJ102V ERJ-6GEYJ102V ERJ-6ENF51R1V ERJ-3GEYJ105V EVQPAE04M 435668-7 TX1099 NA NA MMC2107CFCV33 CY62128V XC2S50-5TQ144C MAX1792EUA25 DS26502L NC7SZ86 NC7SZ86 MAX3233E XCF01SV020C MAX1675EUA EC1-8.000M NTH069A3-6.312 NTH039A3-2.0480 NTH039A3-1.5440
3 of 30
DS26502DK
BOARD FLOORPLAN
USER SWITCHES DS26502 RESET
GND
SYSTEM LEDs
SRAM (264KB) PROTOTYPE AREA
VCC SYSTEM RESET OnCe JTAG DS26502 TESTPOINTS
MICROCONTROLLER
NETWORK CONNECTION
RS232
DS26502 BITS ELEMENT
TX
USER LEDs
FPGA
DS26502 TESTPOINTS
RX
NETWORK CONNECTION
JTAG CONFIG
FPGA STATUS & CONFIG
OSCILLATORS T1, E1, 6312MHZ + BNC DS26502 LEDs
ERRATA
* * RCLK did not get connected to FPGA. A jumper wire has been run from RCLK to TP10 to provide the connection. Silkscreen for J3.4 is incorrect. Silkscreen reads "JTDIMMC2017" and should read "JTDOMMC2107."
ADDITIONS
The following signals have been connected to Testpoints via the FPGA: * * * TP6 is driven with data present at the TS_8K_4 pin of the DS26502 TP7 is driven with the 400Hz signal mentioned in the TS_8Ksrc register (page 16). TP8 is driven with the 8KHz signal mentioned in the TS_8Ksrc register (page 16).
4 of 30
DS26502DK
BASIC OPERATION
This design kit relies upon several supporting files, which are available for downloading on our website at www.maxim-ic.com/telecom. See the DS26502DK QuickView data sheet for these files.
Hardware Configuration
* * * Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V. DIP switches are unused and can be in either the ON or OFF position with exception for the Flash programming switch, which should be OFF. From the Programs menu, launch the host application named ChipView.exe. Run the ChipView application. If the default installation options were used, click the Start button on the Windows toolbar and select Programs (R) ChipView (R) ChipView.
General
* Upon power-up the RLOS and RLOF LEDs (red) will be lit, the INT LED (red) will not be lit, and Status LED (DS10 red/green bicolor) will be green.
Quick Setup (Register View)
* * * * The PC will load ChipView offering a choice among DEMO MODE, REGISTER VIEW, and TERMINAL MODE. Select Register View. The program will then request a definition file. Select DS26502DC_FPGA.def. Through the `links' section, this will also load DS26502.def. The Register View Screen will appear, showing the register names, acronyms, and values for the DS26502. Predefined Register settings for several functions are available as initialization files. * ini files are loaded by selecting the menu File(R)Reg ini File(R)Load ini File. * Load the ini file "CompositeClock.ini." * Load the ini file "DS26502FPGA_2048Clks.ini," which sets the DS26502 in Intel nonmultiplexed mode with MCLK driven at 2.048MHz. * After loading the ini files the following may be observed: * The RLOS and RLOF LEDs extinguishes upon external loopback. * The part begins operating in composite clock mode.
Miscellaneous
* * Clock frequencies and certain pin bias levels are provided by a register-mapped FPGA. The definition file for this FPGA is named DS26502DC_FPGA.def. The FPGA register definitions are located on page 6. A drop-down menu on the top of the screen allows for switching between definition files. All files referenced above are available for download as described in the section marked "BASIC OPERATION."
*
5 of 30
DS26502DK
ADDRESS MAP
Device address space (DS26502 and FPGA) begins at 0x81000000. All offsets given below are relative to the beginning of the device address space (shown above).
Table 1. Device Address Map
OFFSET 0x0000 to 0x0030 0x8000 to 0x80ff DEVICE FPGA DESCRIPTION Board identification and clock/signal routing
DS26502 T1/E1/J1 DS26502 T1/E1/J1 BITS element BITS element
Registers in the FPGA may be easily modified using the ChipView host-based user interface software along with the definition file named "DS26502DC_FPGA.def".
FPGA Register Map
Table 2. FPGA Register Map
OFFSET 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0007 0x09-0x10 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F 0x0020 0x0021 REGISTER NAME BID Unused XBIDH XBIDM XBIDL BREV AREV PREV BUSMO Unused LEVEL1 LEVEL2 LEVEL3 LEVEL4 LEVEL5 LEVEL6 LEVEL7 LEVEL8 LEVEL9 LEVEL10 Unused TSERsrc MCLKsrc TCLK TS_8K Unused Unused TYPE Read only -- Read only Read only Read only Read only Read only Read only Read only -- Control Control Control Control Control Control Control Control Control Control -- Control Control Control Control -- -- DESCRIPTION BOARD ID -- HIGH NIBBLE EXTENDED BOARD ID MIDDLE NIBBLE EXTENDED BOARD ID LOW NIBBLE EXTENDED BOARD ID BOARD FAB REVISION BOARD ASSEMBLY REVISION PLD REVISION BUS MODE INFORMATION -- DS26502 pin settings (THZE, BTS-HBE, BIS1, BIS0) DS26502 pin settings (RMODE3, RMODE2, RMODE1, RMODE0) DS26502 pin settings (RSM, RITD) DS26502 pin settings (TSM, TITD) DS26502 pin settings (TCSS1, TCSS0) DS26502 pin settings (TMODE3, TMODE2, TMODE1, TMODE0) DS26502 pin settings (L2, L1, L0) DS26502 pin settings (TAIS, RLB) DS26502 pin settings (MPS1, MPSO) DS26502 pin settings (JAMUX, E1TS) -- DS26502 TSER source selection DS26502 MCLK source selection DS26502 TCLK source selection DS26502 TS_8K source selection -- -- 6 of 30
DS26502DK
FPGA ID Registers
BID: BOARD ID (Offset = 0x0000) BID is read only with a value of 0xD. XBIDH: HIGH NIBBLE EXTENDED BOARD ID (Offset = 0x0002) XBIDH is read only with a value of 0x0. XBIDM: MIDDLE NIBBLE EXTENDED BOARD ID (Offset = 0x0003) XBIDM is read only with a value of 0x1. XBIDL: LOW NIBBLE EXTENDED BOARD ID (Offset = 0x0004) XBIDL is read only with a value of 0x6. BREV: BOARD FAB REVISION (Offset = 0x0005). BREV is read only and displays the current fab revision. AREV: BOARD ASSEMBLY REVISION (Offset = 0x0006) AREV is read only and displays the current assembly revision. PREV: PLD REVISION (Offset = 0x0007) PREV is read only and displays the current PLD firmware revision.
FPGA Status Registers
Register Name: BUSMO Register Description: DS26502 Bus Mode Register Offset: 0x0011
Bit # Name Default 7 LevCPOL -- 6 LevCPHA -- 5 HW -- 4 SPI -- 3 INMUX -- 2 IMUX -- 1 MNMUX -- 0 MMUX --
The FPGA derives values in the BUSMO register from the levels present at the DS26502 pins.
Bit 7: LevCPOL. When set the DS26502 CPOL pin is high. Note: This pin is called A3/CPOL/L1 in parallel/serial/hardware modes. Bit 6: LevCPHA. When set the DS26502 CPHA pin is high. Note: This pin is called A2/CPHA/L0 in parallel/serial/hardware modes. Bit 5: HW. When set the DS26502 is in hardware mode. Bit 4: SPI. When set the DS26502 is in SPI (3-wire) mode. Bit 3: INMUX. When set the DS26502 is in Intel nonmultiplexed mode. Bit 2: IMUX. When set the DS26502 is in Intel multiplexed mode. Bit 1: MNMUX. When set the DS26502 is in Motorola nonmultiplexed mode. Bit 0: MMUX. When set the DS26502 is in Motorola multiplexed mode.
7 of 30
DS26502DK
FPGA Control Registers
The FPGA register set consists of two types of registers: level setting and clock multiplexing. There are 10 registers for tri-state and level-control setting when in hardware mode. The level-setting registers are only valid when the DS26502 is in hardware mode (BIS1:0 = 11). When in nonhardware mode, the FPGA pins affected by the level registers are automatically either tri-stated, or assume an alternate function (e.g., they function as address databus pins or SPI pins). Exceptions are given with the register descriptions.
Register Name: LEVEL1 Register Description: DS26502 Pin Settings (THZE, BTS, BIS1, BIS0) Register Offset: 0x0011
Bit # Name Default 7 THZEtri 0 6 THZE_Lev 0 5 BTStri 0 4 BTS_Lev 0 3 BIS1tri 0 2 BIS1_Lev 0 1 BIS0tri 0 0 BIS0_Lev 1
Note: This register is only valid in ALL modes (many of the level registers are only valid in hardware mode).
Bits 7 and 6: DS26502 THZE Tri-State and Level (THZEtri and THZE_Lev) 00 = FPGA drives THZE with 3.3V 01 = FPGA drives THZE with 0V 1x = FPGA tri-states THZE pin Bit 5 and 4: DS26502 BTS Tri-State and Level (BTStri and BTS_Lev) 00 = FPGA drives BTS with 3.3V 01 = FPGA drives BTS with 0.0V 1x = FPGA tri-states BTS pin Bits 3 and 2: DS26502 BIS1 Tri-State and Level (BIS1tri and BIS1_Lev) 00 = FPGA drives BIS1 with 3.3V 01 = FPGA drives BIS1 with 0.0V 1x = FPGA tri-states BIS1 pin Bits 1 and 0: DS26502 BIS0 Tri-State and Level (BIS0tri and BIS0_Lev) 00 = FPGA drives BIS0 with 3.3V 01 = FPGA drives BIS0 with 0.0V 1x = FPGA tri-states BIS0 pin
8 of 30
DS26502DK
Register Name: LEVEL2 Register Description: DS26502 Pin Settings (RMODE3, RMODE2, RMODE1, RMODE0) Register Offset: 0x0012
Bit # Name Default 7 RMODE3 tri 0 6 RMODE3 _Lev 0 5 RMODE2 tri 0 4 RMODE2 _Lev 0 3 RMODE1 tri 0 2 RMODE1 _Lev 0 1 RMODE0 tri 0 0 RMODE0 _Lev 0
Note: This register is only valid in hardware mode (BIS[1:0] = 11), and is ignored for other modes.
Bits 7 and 6: DS26502 RMODE3 Tri-State and Level (RMODE3tri and RMODE3_Lev) 00 = FPGA drives RMODE3 with 3.3V 01 = FPGA drives RMODE3 with 0.0V 1x = FPGA tri-states RMODE3 pin Bits 5 and 4: DS26502 RMODE2 Tri-State and Level (RMODE2tri and RMODE2_Lev) 00 = FPGA drives RMODE2 with 3.3V 01 = FPGA drives RMODE2 with 0.0V 1x = FPGA tri-states RMODE2 pin Bits 3 and 2: DS26502 RMODE1 Tri-State and Level (RMODE1tri and RMODE1_Lev) 00 = FPGA drives with RMODE1 3.3V 01 = FPGA drives with RMODE1 0.0V 1x = FPGA tri-states RMODE1 pin Bits 1 and 0: DS26502 RMODE0 Tri-State and Level (RMODE0tri and RMODE0_Lev) 00 = FPGA drives RMODE0 with 3.3V 01 = FPGA drives RMODE0with 0.0V 1x = FPGA tri-states RMODE0 pin
Register Name: LEVEL3 Register Description: DS26502 Pin Settings (RSM, RITD) Register Offset: 0x0013
Bit # Name Default 7 -- 0 6 -- 0 5 RSMtri 0 4 RSM _Lev 0 3 -- 0 2 -- 0 1 RITDtri 0 0 RITD_Lev 0
Note: This register is only valid in hardware mode (BIS[1:0] = 11), and is ignored for other modes.
Bits 5 and 4: DS26502 RSM Tri-State and Level (RSMtri and RSM _Lev) 00 = FPGA drives RSM with 3.3V 01 = FPGA drives RSM with 0.0V 1x = FPGA tri-states RSM pin Bits 1 and 0: DS26502 RITD Tri-State and Level (RITDtri and RITD_Lev) 00 = FPGA drives RITD with 3.3V 01 = FPGA drives RITD with 0.0V 1x = FPGA Tristates RITD pin
9 of 30
DS26502DK
Register Name: LEVEL4 Register Description: DS26502 Pin Settings (TSM, TITD) Register Offset: 0x0014
Bit # Name Default 7 -- 0 6 -- 0 5 TSMtri 0 4 TSM_Lev 0 3 -- 0 2 -- 0 1 TITDtri 0 0 TITD_Lev 0
Note: This register is only valid in hardware mode (BIS[1:0] = 11), and is ignored for other modes.
Bits 5 and 4: DS26502 TSM Tri-State and Level (TSMtri and TSM_Lev) 00 = FPGA drives TSM with 3.3V 01 = FPGA drives TSM with 0.0V 1x = FPGA tri-states TSM pin Bits 1 and 0: DS26502 TITD Tri-State and Level (TITDtri and TITD_Lev) 00 = FPGA drives TITD with 3.3V 01 = FPGA drives TITD with 0.0V 1x = FPGA tri-states TITD pin
Register Name: LEVEL5 Register Description: DS26502 Pin Settings (TCSS1, TCSS0) Register Offset: 0x0015
Bit # Name Default 7 -- 0 6 -- 0 5 TCSS1tri 0 4 TCSS1_Lev 0 3 -- 0 2 -- 0 1 TCSS0tri 0 0 TCSS0_Lev 0
Note: This register is only valid in hardware mode (BIS[1:0] = 11), and is ignored for other modes.
Bits 5 and 4: DS26502 TCSS1 Tri-State and Level (TCSS1tri and TCSS1_Lev) 00 = FPGA drives TCSS1 with 3.3V 01 = FPGA drives TCSS1 with 0.0V 1x = FPGA tri-states TCSS1 pin Bits 1 and 0: DS26502 TCSS0 Tri-State and Level (TCSS0tri and TCSS0_Lev) 00 = FPGA drives TCSS0 with 3.3V 01 = FPGA drives TCSS0with 0.0V 1x = FPGA tri-states TCSS0 pin
10 of 30
DS26502DK
Register Name: LEVEL6 Register Description: DS26502 Pin Settings (TMODE3, TMODE2, TMODE1, TMODE0) Register Offset: 0x0016
Bit # Name Default 7 TMODE3 tri 0 6 TMODE3 _Lev 0 5 TMODE2 tri 0 4 TMODE2 _Lev 0 3 TMODE1 tri 0 2 TMODE1 _Lev 0 1 TMODE0 tri 0 0 TMODE0 _Lev 0
Note: This register is only valid in hardware mode (BIS[1:0] = 11), and is ignored for other modes.
Bits 7 and 6: DS26502 TMODE3 Tri-State and Level (TMODE3tri and TMODE3_Lev) 00 = FPGA drives TMODE3 with 3.3V 01 = FPGA drives TMODE3 with 0.0V 1x = FPGA tri-states TMODE3 pin Bits 5 and 4: DS26502 TMODE2 Tri-State and Level (TMODE2tri and TMODE2_Lev) 00 = FPGA drives TMODE2 with 3.3V 01 = FPGA drives TMODE2 with 0.0V 1x = FPGA tri-states TMODE2 pin Bits 3 and 2: DS26502 TMODE1 Tri-State and Level (TMODE1tri and TMODE1_Lev) 00 = FPGA drives with TMODE1 3.3V 01 = FPGA drives with TMODE1 0.0V 1x = FPGA tri-states TMODE1 pin Bits 1 and 0: DS26502 TMODE0 Tri-State and Level (TMODE0tri and TMODE0_Lev) 00 = FPGA drives TMODE0 with 3.3V 01 = FPGA drives TMODE0with 0.0V 1x = FPGA tri-states TMODE0 pin
11 of 30
DS26502DK
Register Name: LEVEL7 Register Description: DS26502 Pin Settings (L2, L1, L0) Register Offset: 0x0017
Bit # Name Default 7 -- 0 6 -- 0 5 L2tri 0 4 L2_Lev 0 3 L1tri 0 2 L1_Lev 0 1 L0tri 0 0 L0_Lev 0
Note: Settings for L2 are only valid in hardware mode (BIS[1:0] = 11), and ignored for other modes. In serial mode (BIS[1:0] = 10), L0 and L1 are used to set levels for CPHA and CPOL, respectively.
Bits 5 and 4: DS26502 L2 Tri-State and Level (L2tri and L2_Lev) 00 = FPGA drives L2 with 3.3V 01 = FPGA drives L2 with 0.0V 1x = FPGA tri-states L2 pin Bits 3 and 2: DS26502 L1 Tri-State and Level (L1tri and L1_Lev) 00 = FPGA drives L1 with 3.3V 01 = FPGA drives L1 with 0.0V 1x = FPGA tri-states L1 pin Bits 1 and 0: DS26502 L0 Tri-State and Level (L0tri and L0_Lev) 00 = FPGA drives L0 with 3.3V 01 = FPGA drives L0 with 0.0V 1x = FPGA tri-states L0 pin
Register Name: LEVEL8 Register Description: DS26502 Pin Settings (TAIS, RLB) Register Offset: 0x0018
Bit # Name Default 7 -- 0 6 -- 0 5 TAIS tri 0 4 TAIS_Lev 0 3 -- 0 2 -- 0 1 RLBtri 0 0 RLB_Lev 0
Note: This register is only valid in hardware mode (BIS[1:0] = 11), and is ignored for other modes.
Bits 5 and 4: DS26502 TAIS Tri-State and Level (TAIS tri and TAIS_Lev) 00 = FPGA drives TAIS with 3.3V 01 = FPGA drives TAIS with 0.0V 1x = FPGA tri-states TAIS pin Bits 1 and 0: DS26502 RLB Tri-State and Level (RLBtri and RLB_Lev) 00 = FPGA drives RLB with 3.3V 01 = FPGA drives RLB with 0.0V 1x = FPGA tri-states RLB pin
12 of 30
DS26502DK
Register Name: LEVEL9 Register Description: DS26502 Pin Settings (MPS1, MPSO) Register Offset: 0x0019
Bit # Name Default 7 -- 0 6 -- 0 5 MPS1tri 0 4 MPS1_Lev 0 3 -- 0 2 -- 0 1 MPSOtri 0 0 MPSO_Lev 0
Bits 5 and 4: DS26502 MPS1 Tri-State and Level (MPS1tri and MPS1_Lev) 00 = FPGA drives MPS1 with 3.3V 01 = FPGA drives MPS1 with 0.0V 1x = FPGA tri-states MPS1 pin Bits 1 and 0: DS26502 MPS0 Tri-State and Level (MPSOtri and MPSO_Lev) 00 = FPGA drives MPS0 with 3.3V 01 = FPGA drives MPS0 with 0.0V 1x = FPGA tri-states MPS0 pin
Register Name: LEVEL10 Register Description: DS26502 Pin Settings (JAMUX, E1TS) Register Offset: 0x000A
Bit # Name Default 7 -- 0 6 -- 0 5 JAMUXtri 0 4 JAMUX_Lev 0 3 -- 0 2 -- 0 1 E1TStri 0 0 E1TS_Lev 0
Note: This register is only valid in hardware mode (BIS[1:0] = 11), and is ignored for other modes.
Bits 5 and 4: DS26502 JAMUX Tri-State and Level (JAMUXtri and JAMUX_Lev) 00 = FPGA drives JAMUX with 3.3V 01 = FPGA drives JAMUX with 0.0V 1x = FPGA tri-states JAMUX pin Bits 1 and 0: DS26502 E1TS Tri-State and Level (E1Tstri and E1TS_Lev) 00 = FPGA drives E1TS with 3.3V 01 = FPGA drives E1TS with 0.0V 1x = FPGA tri-states E1TS pin
13 of 30
DS26502DK
Register Name: TSERsrc Register Description: DS26502 TSER Pin Source Register Offset: 0x001C
Bit # Name Default 7 -- 0 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 ZEROS 0 1 ONES 1 0 RSER 0
Note: Only one bit in this register should be set at a time. Setting multiple bits tri-states the FPGA pin connected to TSER. Setting to 0 also tri-states this pin.
Bit 2: ZEROS. When set DS26502_TSER 0.0V. Bit 1: ONES. When set DS26502_TSER 3.3V. Bit 0: RSER. When set DS26502_TSER DS26502_TSER.
Register Name: MCLKsrc Register Description: DS26502 MCLK Pin Source Register Offset: 0x001D
Bit # Name Default 7 -- 0 6 -- 0 5 -- 0 4 -- 0 3 ZERO 0 2 EXT 0 1 T1 1 0 E1 0
Note: Only one bit in this register should be set at a time. Setting multiple bits tri-states the FPGA pin connected to MCLK. Setting to 0 also tri-states this pin.
Bit 3: ZERO. When set DS26502_ MCLK 0.0V. Bit 2: EXT. When set DS26502_ MCLK External_Osc (BNC connector). Bit 1: T1. When set DS26502_ MCLK T1_OSC (1.544MHz). Bit 0: E1. When set DS26502_ MCLK E1_OSC (2.048MHz).
14 of 30
DS26502DK
Register Name: TCLKsrc Register Description: DS26502 TCLK Pin Source Register Offset: 0x001E
Bit # Name Default 7 -- 0 6 EXT 0 5 T1 1 4 E1 0 3 64KHZ 0 2 6312 0 1 PLL 0 0 RCLK 0
Note: Only one bit in this register should be set at a time. Setting multiple bits tri-states the FPGA pin connected to TCLK. Setting to 0 also tri-states this pin.
Bit 6: EXT. When set DS26502_ TCLK External_Osc (BNC connector). Bit 5: T1. When set DS26502_ TCLK T1_OSC (1.544MHz). Bit 4: E1. When set DS26502_ TCLK E1_OSC (2.048MHz). Bit 3: 64KHZ. When set DS26502_ TCLK 64kHz clock. Bit 2: 6312. When set DS26502_ TCLK 6312kHz clock. Bit 1: PLL. When set DS26502_ TCLK DS26502_PLL. Bit 0: RCLK. When set DS26502_ TCLK DS26502_RCLK.
Register Name: TS_8Ksrc Register Description: DS26502 TS_8K Pin Source Register Offset: 0x001F
Bit # Name Default 7 -- 0 6 -- 0 5 -- 0 4 EXT 0 3 _8KHz 0 2 400HZ 0 1 400HZ_502 1 0 RS_8K 0
Note: Only one bit in this register should be set at a time. Setting multiple bits tri-states the FPGA pin connected to TS_8K. Setting to 0 also tri-states this pin.
Bit 4: EXT. When set DS26502_TS_8K External_Osc (BNC connector). Bit 3: _8KHz. When set DS26502_TS_8K 8kHz (derived by FPGA). Bit 2: 400HZ. When set DS26502_TS_8K 400Hz clock (derived by FPGA). Bit 1: 4KHZ_502. When set DS26502_TS_8K DS26502_400hz. Bit 0: RS_8K. When set DS26502_TS_8K RS_8K.
15 of 30
DS26502DK
DS26502 INFORMATION
For more information about the DS26502, consult the DS26502 data sheet available on our website at www.maxim-ic.com/DS26502. Software downloads are also available for this demo kit.
DS26502DK INFORMATION
For more information about the DS26502DK, including software downloads, consult the DS26502DK data sheet available on our website at www.maxim-ic.com/DS26502DK.
TECHNICAL SUPPORT
For additional technical support, please e-mail your questions to telecom.support@dalsemi.com.
SCHEMATICS
The DS26502DK schematics are featured in the remaining pages.
16 of 30
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c) 2005 Maxim Integrated Products * Printed USA
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.

▲Up To Search▲

Price & Availability of DS26502DK

	To Download DS26502DK Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .